1. Technical Field
The invention is directed to an imaging system contained in an electronic imager. More specifically, this invention is directed to an imaging system that is adaptively clocked based on a processing schedule.
2. Related Art
Many conventional imaging systems contain a lensing system, through which light passes and strikes an image sensor. The image sensor transforms the incident light into a readable signal that is then processed by interface circuitry. The interface circuitry usually contains functionality for performing row and column scanning of the individual image sensors, an analog to digital (“A/D”) conversion of the signals produced by the image sensors, and some pre-processing circuitry that stores the scanned signals into a simple array.
Typically, the raw image data is then processed by image processing circuitry, which may include a DC restoration, interpolation of pixel data, and image-enhancement processing steps. In addition, in preparation for storage, compression is usually performed on the processed image data. After the processed image data is compressed, the final image data may be stored in a long term storage device or pass to a communication interface for transfer to an external environment. The image processing circuitry usually performs these steps at a much slower rate than the combination of the lensing system, the image sensor circuitry, and the interface circuitry can provide the scanned signals of an image.
Thus, to prevent loss of image data, the capture and preprocessing of images must occur no faster than the post-processing rate. In general, the clocking of the imaging system can only be as fast as the slowest sub-system in the sequential chain of image capture and processing.
This timing discrepancies may also occur between the image processing circuitry and the compression circuitry. Thus, any differences in the timing of the passage of image data between the capture and interface circuitry, between the interface circuitry and the image processing circuitry, and/or between the imaging processing circuitry and the compression circuitry, can create otherwise unnecessary delays in the operation of a typical imager or imaging system.
Moreover, to accommodate one subsystem's processing requirements, a faster and higher power consuming processing unit or circuitry may be selected. Such processing unit or circuitry may be used for multiple sub-system processing at such faster rate which may be unnecessary at times and may utilize higher power than would otherwise be required.